Test register
A test register, in the Intel 80386 and Intel 80486 processors, was a register used by the processor, usually to do a self-test. Most of these registers were undocumented, and used by specialized software. The test registers were named TR3 to TR7. Regular programs don't usually require these registers to work. With the Pentium, the test registers were replaced by a variety of model-specific registers (MSRs).
In the 80386, two test registers, TR6 and TR7, were provided for the purpose of TLB testing. TR6 was the test command register, and TR7 was the test data register. The 80486 provided three additional registers, TR3, TR4 and TR5, for testing of the L1 cache. TR3 was a data register, TR4 was an address register and TR5 was a command register. These registers were accessed by variants of the MOV instruction. A test register may either be the source operand or the destination operand. The MOV instructions are defined in both real-address mode and protected mode. The test registers are privileged resources. In protected mode, the MOV instructions that access them can only be executed at privilege level 0. An attempt to read or write the test registers when executing at any other privilege level causes a general protection exception. Also, those instructions generate invalid opcode exception on most CPUs newer than 80486.
The instruction is encoded in two ways, depending on the flow of data. Moving data from a general purpose register into a test register is encoded as 0F 26 /r (with r/m being the GPR, and reg being the test register). Moving data the other way (i.e. from the test register into a general purpose register) is encoded as 0F 24 /r (with r/m being the GPR, and reg being the test register). Only register-register moves are supported - as such, the "mod" field (top 2 bits) of the instruction's ModR/M byte should be set to 11b. (Setting the "mod" field of the ModR/M byte to anything else than 11b results in undefined behaviour, with different behaviour observed on different processors.)
The test registers and/or associated opcodes were supported in the following x86 processors:
| Processors | , N/a | Cache Test Registers | TLB Test Registers | |||||
|---|---|---|---|---|---|---|---|---|
| TR0 | TR1 | TR2 | TR3 | TR4 | TR5 | TR6 | TR7 | |
| Intel 386 (all models) | No | No | undoc | Yes | ||||
| Intel 486 (all models) | No | Yes | Yes | |||||
| AMD 386 (all models) AMD Élan SC3xx | No | No | ? | Yes | ||||
| AMD 486 (all models) AMD 5x86 AMD Élan SC4xx,SC5xx | No | Yes | Yes | |||||
| IBM 386SLC IBM BL486SLC2/SX2/SX3 | No | Yes | Yes | |||||
| C&T Super386 | No | No | Yes | |||||
| NexGen Nx586 | No | No | Yes | |||||
| Cyrix 486 (all models) | No | Yes | Yes | |||||
| Cyrix 5x86 | No | undoc | Yes | Yes | ||||
| Cyrix 6x86 | No | undoc | Yes | Yes (VSPM) | ||||
| Cyrix 6x86MX, MII | No | undoc | Yes (scratchpad) | Yes | ||||
| VIA Cyrix III | No | ? | Yes (scratchpad) | Yes | ||||
| Cyrix MediaGX NatSemi Geode GX | No | ? | Yes | Yes | ||||
| NatSemi Geode GX2 AMD Geode GX, LX | TR0-TR7 registers present as 32-bit read/write data registers without any cache/TLB test functionality. | |||||||
| IDT WinChip (all models) | Registers not present. The MOV TRx opcodes can be enabled with the WinChip's FCR.EMOVTR bit, but will act as NOPs. | |||||||
| Intel Quark X1000 | No | Yes | Yes | |||||
Sources and credits
This article is adapted from the Wikipedia article “Test register”, written by its contributors and licensed under CC BY-SA 4.0. Fathomly has changed the layout, removed citation markers, navigation and maintenance notices, and adjusted punctuation. This adapted version is shared under the same license. For references, see the original article.
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