Socket SP5
CPU socket for AMD CPUs
Socket SP5 (LGA 6096) is a zero insertion force land grid array CPU socket designed by AMD supporting its Zen 4-based Epyc server processors codenamed Genoa that launched on November 10, 2022.
01History
In June 2017, with the launch of the first generation Epyc server processors, AMD introduced the SP3 socket. The SP3 socket covered three generations of Epyc processors, including Naples, Rome and Milan. AMD's Genoa processors contain up to 96 Zen 4 cores compared to Milan's maximum of 64 cores. In support of Genoa's 96 cores, AMD introduced the SP5 socket with 2022 more contact pins than the SP3 socket to provide greater power delivery and signal integrity. SP5 can provide a peak power of up to 700 W.
The SP5 socket supports Epyc processors codenamed Bergamo, which have up to 128 small Zen 4c cores and were launched on June 13, 2023.
02Features
- Supports 12 channels of DDR5 ECC RAM with 6 TB maximum capacity per socket. Using a dual socket system can allow up to 24 channels of DDR5 ECC RAM with maximum 12 TB RAM capacity.
- Supports 128 lanes of PCI Express 5.0
03Chipsets
Sources and credits
This article is adapted from the Wikipedia article “Socket SP5”, written by its contributors and licensed under CC BY-SA 4.0. Fathomly has changed the layout, removed citation markers, navigation and maintenance notices, and adjusted punctuation. This adapted version is shared under the same license. For references, see the original article.
Images, from Wikimedia Commons:
- Socket SP5 pinmap.svg by QuietRub, CC0
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