Negative flag
In a computer processor the negative flag or sign flag is a single bit in a system status (flag) register used to indicate whether the result of the last mathematical operation produced a value in which the most significant bit (the left most bit) was set. In a two's complement interpretation of the result, the negative flag is set if the result was negative.
For example, in an 8-bit signed number system, -37 will be represented as 1101 1011 in binary (the most significant bit, or sign bit, is 1), while +37 will be represented as 0010 0101 (the most significant bit is 0).
The negative flag is set according to the result in the x86 series processors by the following instructions (referring to the Intel 80386 manual):
- All arithmetic operations except multiplication and division
- Compare instruction, CMP (equivalent to subtract instructions without storing the result)
- Logical instructions, XOR, AND, OR
- TEST instruction (equivalent to AND instruction without storing the result)
- Two's complement negation, NEG
Sources and credits
This article is adapted from the Wikipedia article “Negative flag”, written by its contributors and licensed under CC BY-SA 4.0. Fathomly has changed the layout, removed citation markers, navigation and maintenance notices, and adjusted punctuation. This adapted version is shared under the same license. For references, see the original article.
Fathomly is not affiliated with or endorsed by the Wikimedia Foundation. Spotted a problem? Tell us.