Encyclopedia
MCST-R1000
The MCST R1000 (Russian: МЦСТ R1000) is a 64-bit microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by MCST.
During development this microprocessor was designated as MCST-4R.
01MCST R1000 Highlights
- implements the SPARC V9 instruction set architecture (ISA)
- quad-core
- core specifications:
- in-order, dual-issue superscalar
- 7-stage integer pipeline
- 9-stage floating-point pipeline
- VIS extensions 1 and 2
- Multiply-accumulate unit
- 16 KB L1 instruction cache (parity protection)
- 32 KB L1 data cache (parity protection)
- size 7.6 mm2
- shared 2MB L2 cache (ECC protection)
- integrated memory controller
- integrated ccNUMA controller
- 1 GHz clock rate
- 90 nm process
- die size 128 mm2
- ~150 million transistors
- power consumption 15W
Sources and credits
This article is adapted from the Wikipedia article “MCST-R1000”, written by its contributors and licensed under CC BY-SA 4.0. Fathomly has changed the layout, removed citation markers, navigation and maintenance notices, and adjusted punctuation. This adapted version is shared under the same license. For references, see the original article.
Images, from Wikimedia Commons:
- MCST-4R FPGA prototype.gif by -=HyPeRzOnD=- (talk), CC-BY-SA-2.5
- MCST-4R core.gif by -=HyPeRzOnD=- (talk), CC BY 3.0
- MCST-4R pipeline.gif by -=HyPeRzOnD=- (talk), CC BY-SA 3.0
- MCST-4R diagram.gif by -=HyPeRzOnD=- (talk), CC BY 3.0
- MCST-4R ccNUMA system.gif by -=HyPeRzOnD=- (talk), CC BY-SA 3.0
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