Load-store architecture
Type of instruction set architecture
In computer engineering, a load-store architecture (or a register-register architecture) is an instruction set architecture that divides instructions into two categories: memory access (load and store between memory and registers) and ALU operations (which only occur between registers).
Some RISC architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are load-store architectures.
For instance, in a load-store approach, both the operands and the destination for an ADD operation must be in registers. This differs from a register-memory architecture (for example, a CISC instruction set architecture such as x86) in which one of the operands for the ADD operation may be in memory while the other is in a register. The earliest example of a load-store architecture was the CDC 6600. Almost all vector processors (including many GPUs) use the load-store approach.
Sources and credits
This article is adapted from the Wikipedia article “Load-store architecture”, written by its contributors and licensed under CC BY-SA 4.0. Fathomly has changed the layout, removed citation markers, navigation and maintenance notices, and adjusted punctuation. This adapted version is shared under the same license. For references, see the original article.
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