Geometry Engine
VLSI chip
The Geometry Engine is an early very large scale integrated circuit (VLSI) vector processor designed for 3D computer graphics by Jim Clark and Marc Hannah at Stanford University under ARPA contract.
The Geometry Engine was initially implemented as a 40-pin chip, capable of multiplying two four-element vectors every 15 microseconds; one vector represented the coordinates of a vertex in 3D space while the other was typically a portion of a transformation matrix. Clark anticipated that a pipeline of twelve Geometry Engines would comprise a Geometry System "to accomplish 4 × 4 matrix multiplications; line, character, and polygon clipping; and scaling of the clipped results to display device coordinates".
This ASIC chip was first demonstrated in 1981. This processor is the forerunner of modern tensor processors marketed for graphics and artificial intelligence (AI). The Geometry Engine was adopted commercially in Silicon Graphics computer workstations for many years. Silicon Graphics's first product, shipped in November 1983, was the IRIS 1000, a terminal with hardware-accelerated 3D graphics based on the Geometry Engine. It was capable of approximately 6 million operations per second.
Sources and credits
This article is adapted from the Wikipedia article “Geometry Engine”, written by its contributors and licensed under CC BY-SA 4.0. Fathomly has changed the layout, removed citation markers, navigation and maintenance notices, and adjusted punctuation. This adapted version is shared under the same license. For references, see the original article.
Images, from Wikimedia Commons:
- SGI GE25A Geometry Engine die.jpg by Pauli Rautakorpi, CC BY 3.0
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